The code base directory structure is show in the figure below.
The complete Trireme Platform code base can be accessed through its GitHub repository. The platform allows users to quickly instantiate complete working RISC-V multi-core systems with synthesizable RTL and make targeted modifications to fit their needs. The interfaces between hardware components are carefully designed to allow processor subsystems such as the cache hierarchy, cores or individual pipeline stages, to be modified or replaced without impacting the rest of the system. A web-based system configuration (GUI) can be used to rapidly generate different processor configurations. The platform’s RISC-V compiler toolchain wrapper is used to develop software for the cores. The hardware modules are implemented in synthesizable Verilog using no vendor-specific blocks. The platform can be used for both RTL simulation and FPGA based emulation. It provides highly-parameterized, composable RTL modules for fast and accurate exploration of different RISC-V based core complexities, multi-level caching and memory organizations. The platform is designed with a high degree of modularity. The platform includes RTL, example software, a toolchain wrapper, and configuration graphical user interface (GUI). The Trireme Platform contains all the tools necessary for register-transfer level (RTL) architecture design space exploration.
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